Due to their superior electrostatics gate-all-around nanowire channel field effect transistors (e.g., nanowire FETs) are expected to enable density scaling beyond current planar CMOS technology. In its basic form, a nanowire FET includes a source, a drain and one or more nanowire channels between the source and the drain. A gate electrode, which wraps around the one or more nanowire channels, regulates electron flow through the nanowire channel between the source and drain.
The architecture of a nanowire FET, however, presents notable fabrication challenges. “Bottom-up” nanowire devices built from “grown” nanowires may provide a channel surface with fewer defects, while “top-down” nanowire devices built by patterning and etching bulk materials offer the advantage of deterministic size and placement of nanowires. Currently, the top-down approach is the only method that is feasible for making nanowire FETs at high layout density, since deterministic placement is a prerequisite for high density circuits. However, even with deterministic placement, fabrication of nanowires at very tight gate pitch and a high density of a current-carrying surface are challenging. Scaled gate pitch demands gates which are self-aligned to the source contact region and the drain contact region; a high density of a current carrying surface requires that nanowires be placed very close together or stacked. Previous demonstrations of nanowire FETs are all primarily at relaxed layout density, allowing these problems to be sidestepped.
Scaled gate pitch makes contacting nanowires difficult. One common method for contacting top-down patterned nanowires is to use a large silicon source/drain landing pad which is connected to multiple nanowires. Landing pads provide mechanical stability during processing, simplify the device contacting scheme and can reduce external resistance. However, the landing pads have to be precisely aligned with the gate in order to achieve a highly scaled gate pitch (in the case of logic layouts using minimum gate pitch) and to minimize variations in extrinsic resistance and parasitic capacitance. Properly and consistently aligning the landing pads with the gate is nearly impossible at required gate pitches unless a self-aligned scheme is utilized. As a result, alternate schemes that do not use landing pads have been proposed. Simply eliminating landing pads results in nanowire source/drain regions. In this case, each nanowire in the source/drain region has to be individually contacted. Because nanowires are expected to be at a smaller pitch than contact vias for a high layout density technology, nanowire source/drain regions need to be contacted by contact bars; contact bars introduce greater complexity in patterning and typically require the insertion of an extra mask layer between the contact bars and the first metal layer.
Epitaxially merged source/drain regions is another solution that has been proposed for contacting multiple nanowires. Epitaxial processes, however, have drawbacks due to their extreme sensitivity to surface chemistry, crystal orientation and growth conditions. For example, with an epitaxial growth process, parasitic growth on the gate has to be prevented, the rest of the device structure has to be protected from aggressive pre-epitaxial cleans, and the faceting and direction of the epitaxial growth has to be controlled to minimize both parasitic capacitance and resistance and to achieve similar growth on differently doped source and drain surfaces.
Achieving a high density of a current carrying surface is the other challenge of making high layout density nanowire FETs. As the diameter of nanowires is reduced to enable better electrostatics, the current carrying surface (or area, in the case of bulk inversion) of each nanowire is reduced as well, meaning that more nanowires need to be placed in closer proximity to each other to achieve the same density of the current carrying surface or area. For example, nanowires with a diameter of 4 nm would need to be placed at a pitch of 12 nm to yield the same effective width as a planar device with the same layout footprint. One way to increase layout density in the width direction is to stack the nanowires vertically, rather than using just one layer of them. This is a solution that is unique to gate-all-around devices such as nanowire FETs.
Cho et al., “Observation of Single Electron Tunneling and Ballistic in Twin Silicon Nanowire MOSFETS (TSNWFETS) Fabricated by Top-Down CMOS Process”, 2006 IEEE discloses a nanowire FET structure including two silicon nanowires that are spaced apart from each other in the horizontal direction. Specifically, Cho et al. discloses a horizontally spaced apart twin nanowire-containing FinFET that does not use advanced lithography. The current carrying density of the horizontally spaced apart twin nanowire-containing structure provided in Cho et al. is limited and, as further scaling continues, a further decrease in current carrying density will be observed using the structure provided in Cho et al.
Therefore, a nanowire FET structure and a method for fabrication thereof that improves the device's contacting scheme and scalability, while increasing the device's current carrying density would be desirable.